The present invention relates to an information processor such as a personal computer or a work station, and more particularly to an information processing system in which a plurality of internal buses are hierarchically connected through a bus adaptor or bus converter.
The prior art concerning a computer system including a plurality of internal buses hierarchically connected through a bus adaptor (or bus converter) has been disclosed in JP-A-5-233528.
In the prior art, it is generally known that in order to prevent the transfer by a low-speed I/O module from disturbing the transfer for a low-speed processor memory, independent buses including a processor bus, a system bus and an I/O bus are hierarchically connected to configure a system. The adjacent buses are connected by a bus adaptor (or bus converter). In a general information processor, it is generally known that the protocols of connected buses are different. Therefore, a protocol conversion processing is performed in the bus converter.
In the case where an application handling multimedia, especially, moving images is performed by an information processor such as a personal computer, the handling of a large amount of data may cause the case where the supply of data to be processed from the I/O side to a CPU or a main memory is not in time due to an overhead time for protocol conversion resulting from the hierarchization of buses. On the other hand, in the case where data processed by the CPU or the main memory is to be transferred to a display unit provided on the I/O bus side, there is also a possibility that the display at a fixed transfer rate becomes impossible. When a processing such as the compression/decompression of a moving image is taken into consideration, it may further be considered that the processing capacity of the CPU itself is insufficient even if the supply of data from the I/O side is in time.
An object of the present invention is to provide an information processing system in which in the case of an application handling multimedia, in particular, moving images are produced by an information processor such as a personal computer, and a load imposed on a CPU is distributed to realize a required processing performance with the conventional CPU and bus performances. More particularly, an object of the present invention is to provide a low-cost information processing system in which a plurality of internal buses are hierarchically connected through a bus adaptor and an application handling multimedia, in particular, moving images, is performed by an information processor such as a personal computer and in which a processing load of a CPU is reduced, making it possible to prevent the lowering of a throughput caused by a low-speed bus such as a system bus.
To attain the above object, one aspect of the present invention provides an information processing system in which a processing unit capable of performing an operation processing and an information processing is provided in a bus converter (called a bus adaptor of the information processing system) hierarchically connecting a plurality of internal buses, whereby a part of processings performed by a CPU and an I/O module in the conventional system can be taken over by the bus converter in parallel to the transfer of data.
Since the processing unit is provided in the bus converter, as mentioned above, the frequency of transfer in bus hierarchy transition is reduced in comparison with the case where the transfer of data before operation and the result of operation is made between the CPU bus side module, such as a CPU or a main memory, and the system bus side module such as a graphic device performing the high-speed processing of an MPEG moving image. Thereby, a load imposed on the buses can be reduced. Namely, an overhead time for data transfer is reduced, thereby improving the total performance of the system.
Also, since the bus converter hierarchically connecting the buses, by itself, takes over a portion of an operation for data to be processed, processings to be performed are prevented from concentrating on the CPU or the system bus side I/O module (such as a graphic device), thereby making it possible to reduce the costs of individual parts used in the system or to supplement a system performance even if a low-cost CPU is used.
Further, since a processing unqualified for the CPU, for example a bit operation, can be performed by a dedicated hardware provided in the bus converter or bus adaptor, the information processing capability can also be improved.
Other objects, features and advantages of the present invention will become apparent from reading of the following description of embodiments taken in conjunction with the accompanying drawings.